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· Professional Profile |
On-Site WorkshopsSome of these workshops are given as seminars and tutorials, sometimes in abbreviated and/or different format, at various industry conferences. For scheduled public seminars go to Public Seminars. 1. Full-Day Course - "Pb-Free Soldering Processes-Survival, Quality, Reliability" The switch to lead-free (LF) solders raises a number of issues and problems regarding the manufacture, processing, and reliability of electronic products using Pb-free solders. The threat to the reliability of electronic products comes from three sources: (1) solder joint reliability, (2) printed circuit board (PCB) survival during soldering and long-term reliability, and (3) component survival of soldering processes. The very survival of the electronic assemblies is threatened by the high temperatures required for most of the lead-free soldering processes. The various failure modes that have been observed will be high-lighted, their underlying damage mechanisms will be discussed, and solution options will be offered. The properties of Pb-free solders, particularly SAC solders, can cause processing issues, such as high metal dissolution rates, higher stresses due to thermal expansion mismatches, higher soldering temperatures, will be examined together with their possible impact on solder joint quality as well as assembly damage. Given the high temperatures required for most of the Pb-free soldering processes, the survival of the PCBs and components during the assembly process need to be assured by design, material choice, and processing steps. The PCB and component resin systems need to be able to survive the soldering processes without thermal degradation and delamination. These issues will be discussed in detail. Assemblies that seemingly have successfully survived the soldering processes, may contain latent defects leading to early filed failures due to inadequate quality produced by the loading processing conditions. Only if one is aware of the possibilities is it possible to take steps to prevent these latent defects. Except for increased processing issues, LF-solder joint creep-fatigue reliability has been shown not to be dramatically different from the reliability of SnPb solder joints, at least for accelerated testing. Predicting solder joint reliability for product is still not fully established; however, Design-for-Reliability measures to be taken will be discussed. 2. Half-Day Workshop - "Solder Joint Reliability-Part 1: Adequate reliability of surface mount solder attachments can only be assured with a 'Design for Reliability' based on solder joint behavior and the underlying fatigue damage mechanisms. The consistency of the processing and the quality of the resulting electronic assemblies, while of course necessary, are not sufficient for reliability. Reliability design needs to consider the field use environment, the product design life, as well as the acceptable failure risk level. The complex nature of the interacting mechanisms underlying thermally induced solder joint fatigue combined with the highly temperature-, time-, and stress-dependent behavior of solder will be explored. In this course the issues of quality, manufacturability, and reliability are put into context; the nature of the reliability hazard and the pertinent design parameters and material properties are examined; a solder fatigue model is developed based on experimental results; an acceleration model to extrapolate the results from accelerated reliability tests to reliability predictions for the service environment is derived; accelerated fatigue testing to establish proper reliability data bases is discussed in the context of highly accurate low-acceleration and less accurate high-acceleration tests; electronic product use categories of different environmental severity are defined and appropriate accelerated testing regimens are suggested; the manifestation of solder joint failure and its effect on electrical functionality are experimentally demonstrated using a severely fatigued test board from the IEEE Compliant Lead Task Force program. The reliability information underlying the industry documents such as IPC-9701 "SMT Solder Joint Reliability Qualification and Performance Standard," IPC-SM-785 "Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments," IPC-D-279 "Design Guidelines for Reliable Surface Mount Technology Printed Board Assemblies," and ANSI/IPC J-STD-013 "Implementation of Ball Grid Array and Other High Density Technology," will be discussed in detail. Numerical examples are being worked through to give the attendees hands-on experience in the use of these concepts. The attendees of the course will be able to estimate the reliability of the solder attachments of these packages and optimize the assembly design to achieve adequate reliability for their electronic assemblies. Failure mode and root cause analyses are discussed in Part 2 of this course series, and accelerated reliability testing and product quality screening procedures in Part 3. Reliability issues and information for lead-free (LF) solders are discussed in Part 4. While the four parts are complementary in covering solder joint reliability issues, each part is self-contained. 3. Half-Day Workshop- "Solder Joint Reliability-Part 2: Adequate reliability of surface mount solder attachments can only be assured with a 'Design for Reliability' based on solder joint behavior and the underlying fatigue damage mechanisms as discussed in Part 1. The consistency of the processing and the quality of the resulting electronic assemblies is, of course, also necessary to assure reliability. In this course the issues of quality, manufacturability, and reliability are put into context; failure mode analyses to gain an understanding of the responsible damage mechanisms and to take preventative design measures are explained and demonstrated on hand of numerous photos, illustrations, and cross-sections of solder joints failed in both field operation and during accelerated reliability testing; the manifestation of solder joint failures and their effects on electrical functionality are experimentally demonstrated using a severely fatigued test board from the IEEE Compliant Lead Task Force program using an Event Detector. The basic differences between creep-fatigue-based solder joint failures and brittle fractures due to interfacial problems are illustrated and explained; this includes the so-called 'Black Pad' problems with ENIG metallizations. The attendees of the course will be able to determine the root cause(s) and damage mechanism(s) underlying the solder joint failures of these packages and optimize the assembly design and assembly processes to achieve adequate reliability for their electronic assemblies. The fundamentals of solder joint reliability are discussed in Part 1 of this course, and accelerated reliability testing and product quality screening procedures in Part 3. Reliability issues and information for lead-free (LF) solders are discussed in Part 4. While the four parts are complementary in covering solder joint reliability issues, each part is self-contained. 4. Half-Day Workshop- "Solder Joint Reliability-Part 3: Adequate reliability of surface mount solder attachments can only be assured if a 'Design for Reliability-(DfR)' based on solder joint behavior and the underlying fatigue damage mechanisms has been employed, and when appropriate processing produces electronic assemblies of consistently high quality. Reliability design needs to consider the field use environment, the product design life, as well as the acceptable failure risk level. The interacting mechanisms underlying thermally induced solder joint creep-fatigue combined with the highly temperature-, time-, and stress-dependent properties of solder, while rather complex in nature, need to be understood. This understanding leading to appropriate DfR-procedures comes from properly executed accelerated reliability tests. In this course the issues of quality, manufacturability, and reliability are put into context; the nature of the reliability hazard is examined; acceleration models to extrapolate the results from accelerated reliability tests to reliability predictions for the service environment are discussed and compared; accelerated fatigue testing to establish proper reliability data bases is discussed in the context of highly accurate low-acceleration and less accurate high-acceleration tests; electronic product use categories of different environmental severity are defined and appropriate accelerated testing regimens are suggested; the manifestation of solder joint failure and its effect on electrical functionality are experimentally demonstrated using a severely fatigued test board from the IEEE Compliant Lead Task Force program. The reliability information underlying the industry documents, such as IPC-9701 "SMT Solder Joint Reliability Qualification and Performance Standard" and IPC-SM-785 "Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments," will be discussed in detail. Numerical examples are being worked through to give the attendees hands-on experience in the use of these concepts. The attendees of the course will be able to evaluate the results of accelerated reliability tests of the solder attachments and estimate the expected operational reliability for their electronic assemblies. Latent defects in product, which can result from faulty manufacturing processes, are likely to lead to early failures in the field. Screening procedures, such as ESS, to detect latent defects in product, serve a different purpose than accelerated reliability tests and thus need to be designed quite differently. Screening procedures used in the industry will be discussed and evaluated. The fundamentals of solder joint reliability are discussed in Part 1 of this course, and failure mode and root cause analyses are discussed in Part 2. Reliability issues and information for lead-free (LF) solders are discussed in Part 4. While the four parts are complementary in covering solder joint reliability issues, each part is self-contained. 5. Half-Day Workshop- "Solder Joint Reliability-Part 4: The impending switch to lead-free (LF) solders raises a number of issues and problems regarding the manufacture, processing, and reliability of electronic products using LF-solders. Adequate reliability of surface mount solder attachments can only be assured with a 'Design for Reliability' based on solder joint behavior and the underlying fatigue damage mechanisms. The consistency of the processing and the quality of the resulting electronic assemblies, while of course necessary, are not sufficient for reliability. Reliability design needs to consider the field use environment, the product design life, as well as the acceptable failure risk level. The complex nature of the interacting mechanisms underlying thermally induced solder joint fatigue combined with the highly temperature-, time-, and stress-dependent behavior of solder will be explored. These issues are addressed in the four parts of this course. In Part 4 of this course the special reliability threats to the solder attachments themselves as well as to the printed circuit board (PCB) substrates and components coming from the utilization of LF-solders will be discussed. These threats to reliability will be detailed as to the load drivers and the resulting failure modes, and illustrated by pertinent examples and illustrations. Reliability of solder attachments can only be assured with an understanding of all the factors impacting the loading conditions on the solder joints. Solder creep-fatigue behavior as well as the different load drivers such as thermal cycling, vibration, and mechanical shock are explained. The available information for LF-solders, which often is seemingly contradictory, will be put into context with the creep-fatigue behavior of tin-lead (Sn/Pb) solders. The physics-of-failure and failure statistics information underlying the information for Sn/Pb solders in industry documents took over 30 years to develop. The available information for the creep-fatigue behavior LF-solders is as yet inadequate for the determination of acceleration factors and the development of creep-fatigue models. Appropriate testing, which has even more importance given the absence available acceleration factors for LF-solders, to assess the extent of these various reliability threats will be suggested and discussed. Strategies to assure the reliability of the solder attachments, printed circuit boards (PCBs), and components in electronic product subjected to LF-soldering will be explained. Further, issues in the processing of electronic assemblies utilizing LF-solders arising from the higher soldering temperatures and the metallurgy of LF-solders will be highlighted and discussed. The fundamentals of solder joint reliability are discussed in Part 1 of this course series. Failure mode and root cause analyses are discussed in Part 2, and accelerated reliability testing and product quality screening procedures in Part 3. While the four parts are complementary in covering solder joint reliability issues, each part is self-contained. 6. Half-Day Workshop- "Reliability Issues for Lead-Free Soldering: The likely switch to lead-free (LF) solders raises a number of issues and problems regarding the manufacture, processing, and reliability of electronic products using LF-solders. In this course the reliability threats to the solder attachments themselves as well as to the printed circuit board (PCB) substrates and components will be discussed. These threats to reliability will be detailed as to the load drivers and the resulting failure modes, and illustrated by pertinent examples and illustrations. Further, issues in the processing of electronic assemblies utilizing LF-solders arising from the higher soldering temperatures and the metallurgy of LF-solders will be highlighted and discussed. Adequate reliability of surface mount solder attachments can only be assured with an understanding of all the factors impacting the loading conditions on the solder joints. Solder creep-fatigue behavior as well as the different load drivers such as thermal cycling, vibration, and mechanical shock are explained. The available information for LF-solders, which often is seemingly contradictory, will be put into context with the creep-fatigue behavior of tin-lead (Sn/Pb) solders. The physics-of-failure and failure statistics information underlying the information for Sn/Pb solders in industry documents such as IPC-9701 "SMT Solder Joint Reliability Qualification and Performance Standard," IPC-SM-785 "Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments," and IPC-D-279 "Design Guidelines for Reliable Surface Mount Technology Printed Board Assemblies," took over 30 years to develop. The available information for the creep-fatigue behavior LF-solders is as yet inadequate for the determination of acceleration factors and the development of creep-fatigue models. Appropriate testing, which has even more importance given the absence available acceleration factors for LF-solders, to assess the extent of these various reliability threats will be suggested and discussed. Strategies to assure the reliability of the solder attachments, printed circuit boards (PCBs), and components in electronic product subjected to LF-soldering will be explained. 7. One-Day In-Depth Workshop- IPC-9701 was developed to provide an industry standard that allows a meaningful comparison of the solder attachment reliability capability for components soldered to a defined PWB. This standard became necessary, because the absence of such a standard had resulted in some extravagant claims of product reliability based on inappropriate accelerated tests not meeting IPC-SM-785 "Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments." Adequate reliability of surface mount solder attachments can only be assured with an understanding of all the factors impacting the loading conditions on the solder joints. The move to high-density electronic assemblies with small fine-pitch solder joints has necessitated that part of the 'Design for Reliability' be accomplished within the components, e.g., CSPs, themselves. However, different component designs provide varying levels of internal accommodation of the thermal expansion mismatches between the silicon chips and the PWB that are the root-cause of solder joint failures. In this tutorial the reliability threat addressed in IPC-9701 is discussed on hand of various electronic components and their different design parameters and materials. The requirements of the IPC-9701 standard are presented and discussed. Solder fatigue behavior as well as the strain/stress loading due to cyclic thermal excursions are explained. Acceleration transform are compared and used to extrapolate the results from IPC-9701 accelerated reliability tests to reliability predictions for different service environments. The physics-of-failure and failure statistics information underlying IPC-9701 as well as the industry documents IPC-SM-785 "Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments," IPC-D-279 "Design Guidelines for Reliable Surface Mount Technology Printed Board Assemblies," ANSI/IPC J-STD-012 "Implementation of Flip Chip and Chip Scale Technology", and ANSI/IPC J-STD-13," Implementation of Ball Grid Array and Other High Density Technology," will be discussed in detail. Numerical examples are being worked through to give the attendees hands-on experience in the use of these concepts. 8. One-Day Workshop- Plated-through holes and vias (PTHs/PTVs) are subject to interconnect failures due to barrel cracking and inner-layer separation (post separation). Electronic assemblies are subject to severe thermal excursions during processing and assembly and to cyclic thermo-mechanical loading conditions due to system-external temperature variations and imposed operating conditions, as well as due to environmental stress screening (ESS) and burn-in procedures. The severe processing thermal excursions can result in overstress fractures during processing which lead to failures during manufacture or shortly thereafter. The accumulating fatigue damage resulting from the cyclic thermo-mechanical loading and other causes, e.g. vibration, can lead to the premature failure of the plated-through-holes (PTH) and vias (PTV), because fatigue damage accumulates until the material's capability to accommodate it is exhausted. For high-density electronic assemblies high quality and yields, as well as long-term reliability can be assured only by a deliberate design effort that considers the specific damage mechanisms threatening the integrity of the electronic assembly. Knowledge of the loading stresses on of PTH/PTV barrels and the inner-layer interconnects, and of what constitutes typical processing parameters and realistic use environments are the prerequisite for successful 'Design for Manufacturability' and 'Design for Reliability' of high-performance, high-density electronic assemblies. The material in this course incorporates the work by the course leader during his association with Bell Laboratories as well as the results from the IPC-TR-484 "Results of IPC Copper Foil Ductility Round Robin Study," IPC-TR-579 "Round Robin Reliability Evaluation of Small Diameter Plated Through Holes in Printed Wiring Boards," and IPC-TR-486 "Report on Round Robin Study to Correlate Interconnect Stress Test (IST) with Thermal Stress/Microsectioning Evaluations for Detecting the Presence of Inner-Layer Separations." In this workshop the information underlying the industry document IPC-D-279 "Design Guidelines for Reliable In this workshop the issues of quality, manufacturability, and reliability are put into context; the nature of the reliability hazard and the pertinent design parameters and material properties are examined; an analytical technique to estimate the fatigue life of PTH/PTVs is developed based on experimental results and theoretical insights; electronic product use categories of different environmental severity are defined and effective coupon testing-Interconnect Stress Testing (IST [IPC-TM-650, 2.6.26]) and ESS procedures are discussed. A numerical example is being worked through to give the attendees hands-on experience in the use of these concepts. 9. Half-Day Workshop- Plated-through holes and vias (PTHs/PTVs) are subject to interconnect failures due to barrel cracking and inner-layer separation (post separation). Electronic assemblies are subject to severe thermal excursions during processing and assembly and to cyclic thermo-mechanical loading conditions due to system-external temperature variations and imposed operating conditions, as well as due to environmental stress screening (ESS) and burn-in procedures. The severe processing thermal excursions can result in overstress fractures during processing which lead to failures during manufacture or shortly thereafter. The accumulating fatigue damage resulting from the cyclic thermo-mechanical loading and other causes, e.g. vibration, can lead to the premature failure of the plated-through-holes (PTH) and vias (PTV), because fatigue damage accumulates until the material's capability to accommodate it is exhausted. For high-density electronic assemblies high quality and yields, as well as long-term reliability can be assured only by a deliberate design effort that considers the specific damage mechanisms threatening the integrity of the electronic assembly. Knowledge of the loading stresses on of PTH/PTV barrels and the inner-layer interconnects, and of what constitutes typical processing parameters and realistic use environments are the prerequisite for successful 'Design for Manufacturability' and 'Design for Reliability' of high-performance, high-density electronic assemblies. The material in this course incorporates the work by the course leader during his association with Bell Laboratories as well as the results from the IPC-TR-484 "Results of IPC Copper Foil Ductility Round Robin Study," IPC-TR-579 "Round Robin Reliability Evaluation of Small Diameter Plated Through Holes in Printed Wiring Boards," and IPC-TR-486 "Report on Round Robin Study to Correlate Interconnect Stress Test (IST) with Thermal Stress/Microsectioning Evaluations for Detecting the Presence of Inner-Layer Separations." In this workshop the information underlying the industry document IPC-D-279 "Design Guidelines for Reliable Surface Mount Technology Printed Board Assemblies," is discussed. Reliability issues and problems are discussed for the higher soldering temperatures required for lead-free solders. In this workshop the issues of quality, manufacturability, and reliability are put into context; the nature of the reliability hazard and the pertinent design parameters and material properties are examined; an analytical technique to estimate the fatigue life of PTH/PTVs based on experimental results and theoretical insights is developed; electronic product use categories of different environmental severity are defined and effective coupon testing-Interconnect Stress Testing (IST [IPC-TM-650, 2.6.26]) is discussed. 10. One-Day Workshop- The interconnect structures within printed circuit boards (PCBs) have been subject to failures due to PTH/PTV barrel cracking and inner-layer separation (post separation). Electronic assemblies are subject to severe thermal excursions during processing and assembly and to cyclic thermo-mechanical loading conditions due to system-external temperature variations and imposed operating conditions. This has become much more of a problem with the EU-RoHS-mandated move to lead-free soldering, because of the significantly higher soldering temperatures required. The severe processing thermal excursions can result in the thermal decomposition of the PCB base materials leading to both adhesive and cohesive delaminations. Further, overstress fractures during processing which lead to failures during manufacture or shortly thereafter. The accumulating fatigue damage resulting from the cyclic thermo-mechanical loading and other causes, e.g. vibration, can lead to the premature failure of the plated-through-holes (PTH) and vias (PTV). It therefore has become necessary to assure the survivability and reliability of the PCBs by appropriate design measures and material choices. Industry documents, such as IPC-1710 and IPC-9151 address the qualification and capabilities of PCB shops, however, many PCB failures result from inadequate designs even when produced to good quality because of the demands to multiple soldering operations and the higher soldering temperatures necessary for lead-free solder assembly. In this tutorial, recommendations are made in terms of a suggested full set of FAB Notes, as they would appear on a PCB drawing. These notes are discussed one after another as to the reasons for the recommendations and the possible variations in these recommendations. In this tutorial, steps and tests are also recommended to assure the continued quality of PCBs, which of course is also necessary for the survivability and reliability of the PCBs in assembly and operation. 11. Half-Day Executive Briefing- Surface mounting was born of the need for ever increasing electronic packaging and interconnection densities. This also is driving electrical conductor widths and spacings ever narrower, plated-through-hole and via diameters ever smaller, and circuit board thicknesses ever larger. As features and components get smaller, many design, materials, assembly, and processing interactions become critical potential problem areas: manual steps become inadequate to maintain consistency and need to be automated; the effects of even small processing variations on product quality require meticulous automated record keeping; production process windows are narrowed to the point of inadequacy; and the interaction of many materials with often very diverse properties can cause yield and reliability problems. Electronic assemblies are subject to severe thermal excursions during processing and assembly and to cyclic thermo-mechanical loading conditions due to system-external temperature variations and imposed operating conditions, as well as due to environmental stress screening (ESS) and burn-in procedures. The severe processing thermal excursions can result in overstress fractures during processing which lead to failures during manufacture or shortly thereafter. The accumulating fatigue damage resulting from the cyclic thermo-mechanical loading and other causes, e.g. vibration, can lead to the premature failure of the plated-through-hole-vias (PTVs), because fatigue damage accumulates until the material's capability to accommodate it is exhausted. Adequate reliability of surface mount solder assemblies can only be assured with proper up-front design input based on a thorough technical understanding of the underlying issues. The processing capabilities and limitations in one's plant as well as of vendors' facilities need to be considered in a 'Design for Manufacturability' to assure consistent high quality product. The consistency of the processing and the quality of the resulting electronic assemblies, while of course necessary, are not sufficient for reliability. A 'Design for Reliability' needs to consider the field use environment, the product design life, as well as the acceptable failure risk level in the context of the consequences of failure. Significant industry confusion on these issues stems from the very complex and only partially understood nature of the interacting mechanisms underlying in particular thermally induced failures combined with the highly temperature-, time-, and stress-dependent behavior of some of the involved materials, especially solder and polymers. In this briefing, quality, manufacturability, and reliability are put into context and the issues are illustrated using surface mount solder joint reliability and high-aspect-ratio plated-through vias as examples. |
